PhD Course: Spintronic Technology For Energy-Efficient In Memory Computing

Spintronic technology has emerged as a promising technology to address the issues of volatility and static power dissipation resulting from the scaling down of CMOS technology towards the end of Moore’s law.

Magnetic tunnel junction (MTJ) is a prominent spintronic device that combines magnetism and electronics to develop next-generation non-volatile memory (NVM) and hybrid CMOS/MTJ circuits.

The recent developments of full hybrid magnetic/CMOS circuits/systems has further strengthened the potential of this technology for a wide range of applications.

In this context, this course aims to provide an overview of design flow of hybrid CMOS/MTJ circuits using MTJ spintronic devices compatible with conventional CMOS logic.

The course covers the basics of MTJ devices, compact models, and MTJ-based memories and logic-in-memory (LIM) architectures.

The course also highlights the challenges and future prospects of hybrid CMOS/MTJ circuits, which could motivate further research in this domain.

MOD4 room - 5th floor, cube 39C

14/06/2023 (10:30-12:30) - (15:00-17:00)

15/06/2023 (10:30-12:30)

6h - 1,5 CFU