PhD Course: Novel device and architecture concepts for CMOS Logic scaling: a reliability engineer perspective
Published July 10, 2025 - 11:08
- giovedì 17 luglio, dalle 11:00 alle 13:00, Aula DS5, Cubo 41B, 2° Piano
- giovedì 17 luglio, dalle 15:00 alle 17:00, Aula DS5, Cubo 41B, 2° Piano
1 CFU, 4 ore
Teachers:
Jacopo Franco