PhD Course: Advanced methods to design hardware accelerators

Modern applications, like Computer Vision (CV), Internet of Things (IoT), Deep Learning (DL) oriented to image classification, object detection, and segmentation tasks, intelligent autonomous vehicles, smart manufacturing, and many others, demand high computational speed, significant energy efficiency, and flexibility.
For this reason, designing hardware accelerators currently receives a great deal of attention.
This course overviews the main advanced methodologies to design both Application Specific Integrated Circuits (ASICs) and Field-Programmable-Gate-Array (FPGA)-based hardware accelerators suitable to support the above-cited applications.
In particular, design and algorithmic strategies exploitable to reduce the computational complexity of deep learning models
without compromising the achievable accuracy are examined. Moreover, several design techniques oriented to edge computing systems are explored.
The course also provides an overview of techniques currently used to efficiently implement CNN inference on low-power edge devices through data-level approximations, such as quantization and pruning. Some noteworthy state-of-the-art FPGA and ASIC implementations will also be presented.
At the end of this course, students will have a comprehensive knowledge of the main design techniques applicable at circuit-, architecture-, and system-level to hardware-accelerate computationally intensive elaborations. They will also get an understanding of methodologies and tools that can be used in several artificial intelligence applications, also related to their research topics.

2 CFU

• 27 aprile ore 9:00-13:00 e 15:00-19:00 – Laboratorio didattico di elettronica (Cubo 42C - piano terra).