Esteban Garzon

Research Abstract

Spin-transfer torque magnetic RAMs (STT-MRAMs) are gaining popularity thanks to their promising features in terms of integration density, long data retention, almost zero standby power, and full compatibility with CMOS process. STT-MRAMs are among the best candidates to replace conventional semiconductor-based on-chip memories at advanced technology nodes, especially for normally-off applications in the Internet of Things (IoT) scenario. Despite the above favorable properties and the reduced switching current of perpendicular magnetic anisotropy (PMA) devices, the STT-MRAMs scalability still remains challenging. To this aim, one effective strategy concerns the use of double-barrier MTJs (DMTJs) in place of conventional single-barrier MTJs (SMTJs).

The main focus is on the assessment of hybrid CMOS/STT-MTJ circuits for non-volatile (NV) memory and logic applications, such as STT-MRAMs and non-volatile logic gates. STT-MRAMs addressed to NV cache applications is been investigated at nanoscaled technology nodes while using double-barrier MTJs with two reference layers (DMTJs) instead of conventional solution based on single-barrier MTJs (SMTJs). Such studies can be carried out by using a cross-layer simulation platform, which spreads from the device- up to the system-level passing through a circuit-level analysis for different memory bitcell configurations and a memory architecture-level analysis for various cache sizes. This has required an accurate setup of different simulation tools used at different design levels of abstraction. In addition, bit-level NV logic circuits based on hybrid CMOS/STT-MTJ design is also investigated.