Fanny Spagnolo

Research Abstract

In the majority Vision Systems applications, it is necessary to process in real time images and videos. This requirement, joined with the increasing complexity of the processing algorithms, drives the research to new more performing hardware platforms. Currently, the main design solutions are based on Digital Signal Processing, Field Programmable Gate Array (FPGA) devices and Application Specific Integrated Circuit (ASIC) devices. However, these approaches force the designers to choose between an “All Software” or “All Hardware” implementation. Conversely, the proposed methodological approach uses a heterogeneous architecture, which integrates on the same device a CPU and a Programmable Logic section. In this way, it is possible to exploit the synergy between these two devices. In fact, if on one hand we can improve performances as result of the dedicated hardware use, on the other hand we can ensure the system flexibility thanks to the software programming. Clearly, the development of this methodology requires to focus the research activity on two main key points. The first one concerns the communication between the Processing System section (CPU) and the Programmable Logic section (FPGA fabric). This issue must be treated with particular consideration, because we have to ensure that the data transfer times do not become the bottleneck system. The second one refers to Hardware/Software partitioning choice. It is important to provide some criteria about how to divide the tasks among hardware and software, in order to optimize power consumption and/or performances.