Francesco Settino

Advisor: Prof. Felice Crupi

 

Topic: Signal Integrity analysis of Chip-Package-Board for System-on-Chip designs

Abstract: Modern System-on-Chips (SoCs) have many digital, analog and mixed-signal interfaces due to the ever increasing functionality and levels of integration. Signal integrity is a main issue in package and board designs due to the parasitic effects of capacitive/inductive coupling. In general, fast switching signals (aggressors) can induce unwanted disturbances into low activity signals (victims) due to crosstalk effects, which may degrade significantly the overall system performance.

A simulation framework for reliable & accurate prediction of the system level behavior is essential to detect potential specification violation issues in the early phase of the development process. A Methodology to enable optimized design will be investigated, providing guidelines for both on-chip (circuit blocks) & off-chip (Package-Board) designs, in order to full-fill the system level requirements for future generation of complex SoCs.

email: f.settino@dimes.unical.it